The present invention concerns fabrication methods and structures for integrated circuits, particularly methods for making silicon-on-insulator structures.
Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, typically a round slice of silicon called a wafer. The components are then wired, or interconnected, together to define a specific electric circuit, such as a computer processor or memory.
The evolution of integrated circuits has been driven by three principal objectives: reducing size, lowering power consumption, and increasing operating speed. Silicon-on-insulator (SOT) technology--an emerging technology which entails building silicon devices, such as transistors, on an insulative substrate rather than on a silicon substrate as done typically--dramatically advances all three objectives. First, silicon-on-insulator technology provides superior electrical isolation between adjacent components, which, in turn, allows closer component spacing and integrated-circuit size reductions. Second, silicon-on-insulator technology reduces integrated-circuit capacitance, the primary obstacle to faster operating speeds. And third, it enables use of lower operating voltages, which significantly reduces power consumption.
Unfortunately, conventional methods for implementing silicon-on-insulator technology waste costly silicon, and therefore have been commercially viable in only a few high-priced applications. For instance, one conventional method forms an insulative layer on the top surface of a silicon wafer and bonds the entire surface of another silicon wafer onto the insulative layer, essentially sandwiching the insulative layer between the two silicon wafers. This method then wastefully grinds down one of the silicon wafers to a thin silicon layer, yielding one silicon-on-insulator structure at the cost of two silicon wafers.
A similar method, dubbed "smart cut" by its proponents, is a bit more cost effective. The smart-cut method sandwiches an insulative layer between two silicon wafers, but rather than grinding down one of the wafers, it in effect slices off a thick portion of one wafer, leaving a thin slice of silicon covering the entire insulative layer and saving the thick portion for use in another silicon-insulator-silicon sandwich. Thus, the smart-cut method is emerging as a substitute to the bond-and-grind method.
However, the smart-cut method suffers from at least three shortcomings. First, slicing the silicon wafer entails implanting hydrogen ions into the silicon, some of which remain in the bonded silicon after the slicing procedure, and introduce defects into transistors later formed in the silicon. Second, the smart-cut method indiscriminantly bonds a continuous silicon layer to the entire insulative surface, not only to regions where transistors are desired but also to regions where they aren't. The continuity of the silicon layer forces it to buckle and crack during subsequent processing because the insulation and silicon expand and contract at very different rates in response to temperature changes. Third, the continuity also allows silicon between and around intended transistors to form unintended, or parasitic, devices, for example parasitic diodes and transistors, which compromise isolation, performance, and reliability of the intended transistors.
Accordingly, there is a need for more effective methods of making silicon-on-insulator structures.